1. Field of the Invention
The present invention relates to a differential amplifier. More specifically, the present invention is directed to a differential amplifier used in an amplifying circuit of an LCD driver for driving a capacitive load.
2. Description of the Related Art
Nowadays, there is a trend that higher gradation is strongly required in a TFT-LCD (Thin-Film Transistor Liquid Crystal Display) field. That is to say, conventionally, 260,000-color display (64 gradation levels in 6 bits) sufficiently satisfied requirements of the TFT-LCD field. However, currently, 16,780,000-color display (256 gradation levels in 8 bits) is requested in the TFT-LCD field. Moreover, display of 1,024 gradation levels in 10 bits is requested depending on fields. For instance, such a higher gradation display is requested for X-ray image display in a medical field and TV display field. When such a higher gradation display is achieved, an LCD driver circuit becomes more complicated. For example, such a LCD driver is disclosed in Japanese Laid Open Patent Application (JP-P2001-34234A). In this LCD driver, furthermore, a chip area of the driver circuit is increased, resulting in higher cost.
FIG. 1 is a block diagram showing a partial circuit of a conventional LCD driver in which operational amplifiers having two non-inversion inputs are used. Referring now to FIG. 1, the conventional LCD driver is composed of a latch address selector 101, a latch circuit 102, n (n is an integer more than 1) decoders 103, and n operational amplifiers 104. Each of these operational amplifiers 104 has two non-inversion inputs, and constitutes a voltage follower circuit.
Input data D0 to D8 corresponding to 8-bit display data are supplied to the latch circuit 102. Outputs of the latch circuit 102 are supplied to the respective decoders 103. Each of these decoders 103 has two voltage output terminals (Vin1 and Vin2). Voltage outputs (Vin1/Vin2) from the two voltage output terminals of each decoder 103 are supplied to a corresponding one of the operational amplifiers 104. In this circuit, 8-bit 256-gradation voltages are not supplied to one decoder 103, but 129-gradation (=256/2+1) voltages are supplied to the decoder 103. A voltage between the adjacent two voltages is interpolated by the operational amplifiers 104, and 8-bit 256-gradation voltages are outputted as a final output from the operational amplifiers 104.
FIG. 2 is a diagram showing a specific circuit arrangement of one operational amplifier 104 having two non-inversion inputs shown in FIG. 1. Referring to FIG. 2, in the operational amplifier 104, two MOS transistors on an input side are grouped, and one output (Vout) is generated to the two input voltages (Vin1, Vin2). The output voltage (Vout) is V2 in case where the input voltages (Vin1 and Vin2) are equal to a same gradation voltage (for instance, Vin1=Vin2=V2). In case where the input voltages (Vin1 and Vin2) are adjacent gradation voltages (for instance, Vin1=V0 and Vin2=V2), the output (Vout) is substantially equal to an intermediate voltage V1 obtained by combining V0 with V2.
In the 2-input amplifier employed in the conventional driver circuit as shown in FIG. 2, when a difference between the two input voltages Vin1 and Vin2 is relatively small, the output voltage (Vout) is obtained as follows:Vout=(Vin1+Vin2)/2.However, when a difference between the two input voltages becomes large, a deviation from (Vin1+Vin2)/2 becomes larger.
Thus, a high precision driver circuit is desirable without requiring a complex circuit arrangement.
In conjunction with the above description, an interpolation type D-A converter is disclosed in Japanese Laid Open Patent Application (JP-P2001-313568A, see FIG. 10 of this conventional example). This conventional example is used for a TFT LCD driver which is composed of a reference voltage generation circuit which generates a plurality of reference voltages. At least one decoding switch receives the plurality of reference voltages from the reference voltage generation circuit and selects two of the plurality of reference voltages based on a plurality of high bits of a digital image signal. A routing switch is connected with the decoding switch and generates first and second reference voltages based a plurality of low bits of the digital image signal. An interpolation buffer is connected with the routing switch and generates an interpolation analog signal based on the first and second reference voltages.
Also, a driver circuit is disclosed in Japanese Laid Open Patent Application (JP-P2001-343948A). In this conventional example, a gradation voltage generating circuit generates a plurality of gradation voltages which are different in voltage level from each other. A decoder decodes an input data and selects first and second gradation voltages from the plurality of gradation voltages based on the decoding result. An amplifier generates a drive voltage based on the first and second gradation voltages. The amplifier is composed of a first transistor for a differential pair, a second transistor connected with the first transistor for the differential pair, a third transistor connected in parallel to the second transistor, and a switch circuit. The switch circuit carries out a switching operation in a predetermined period between a first state in which the first gradation voltage is transferred to the first transistor and the second gradation voltage is transferred to the second transistor, and a second state in which the second gradation voltage is transferred to the first transistor and the first gradation voltage is transferred to the second transistor.